1. Field of the Invention
The present invention relates generally to a semiconductor memory device and a method of manufacturing the same. More particularly, the invention relates to a semiconductor memory device having an etch stopper formed in a cell region and a method of manufacturing the semiconductor memory device.
A claim of priority is made to Korean Patent Application No. 10-2005-0015371, filed on Feb. 24, 2005, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
As the integration density of semiconductor memory devices increases, contact holes formed in the semiconductor devices become increasingly narrow. As a result, the aspect ratio of the contact holes tends to increase, and therefore contact holes and associated contacts are often required to be formed using multi-step processes.
The integration density of dynamic random access memory (DRAM) devices is typically very high. Because of this, active regions between adjacent gate electrodes in DRAMs are generally so narrow that it is difficult to form contacts connected to the active regions. One approach to forming contacts in narrow regions is to form a hard mask layer and spacers over and around the gate electrodes before forming self aligned contact pads between the gate electrodes. Then, bitline contacts or storage node contacts are formed over the self-aligned contact pads. This approach is often referred to as “self aligned contact technology.”
Typically, the self-aligned contacts have a larger diameter than the bitline contacts or the storage node contacts. However, as the integration density of DRAM devices continues to increase, the diameter of the self-aligned contact pads reduces and approaches the diameter of the bitline and storage node contacts. As a result, slight misalignments between the bitline or storage node contacts and node can cause serious problems in the manufacture of DRAM devices. Illustrations of some common problems are described below in relation to FIG. 1.
Referring to FIG. 1, a conventional semiconductor memory device comprises a semiconductor substrate 10 in which a cell region “A” and a core and peripheral region “B” are defined. A plurality of isolation layers 15 defining active regions 10a are formed in semiconductor substrate 10, and junction regions 25a and 25b are formed between isolation layers 15 in respective cell and core and peripheral regions “A” and “B”.
A first insulating interlayer 30 is formed over semiconductor substrate 10 and a second insulating interlayer 40 is formed over first insulating interlayer 30.
In cell region “A”, a plurality of self-aligned contact pads 35 are formed in first insulating interlayer 30 over junction regions 25a, and a plurality of bitline contact holes 45 are formed in second insulating interlayer 40 to expose self-aligned contact pads 35.
In core and peripheral region “B”, a gate electrode structure 20 is formed in first insulating layer 30 on side junction region 25b and an interconnection contact hole 50 is formed in first and second insulating interlayer 30 and 40 to expose side junction region 25b . Each gate electrode structure 20 comprises a gate insulating layer 16 formed on semiconductor substrate 10, a gate electrode material 17 formed on gate insulating layer 16, a hard mask layer 18 formed over gate electrode material 17, and spacers 19 formed on the sidewall of gate insulating layer 16, gate electrode material 17, and hard mask layer 18.
Typically, the respective diameters of self-aligned contact pads 35 and bitline contact holes 45 are slightly different from each other, or they are slightly misaligned with each other. As a result, portions of first insulating interlayer 30 adjacent to self-aligned contact pads 35 may be removed when bitline contact holes 45 are formed. Due to the partial loss of first insulating interlayer 30, active regions 10a may also be partially removed, causing leakage current in the semiconductor memory device.
Storage node contact holes (not shown) are typically formed after bitlines are formed in bitline contact holes 45. The storage node contact holes are generally formed between the bitlines to contact self-aligned contact pads 35. However, the storage node contact holes are almost inevitably misaligned with the self-aligned contact pads. As a result, the first insulating interlayer 30 is almost inevitably etched when the storage node contact holes are formed, causing further damage to active regions 10a. 
Interconnection contact hole 50 is typically formed in core and peripheral region “B” at the same time when bit line contact holes 45 are formed in cell region “A”. Unfortunately, however, as the integration density of core and peripheral region “B” increases, interconnection contact hole 50 tends to expose more than just junction region 25b. For instance, interconnection contact hole 50 may expose parts of gate electrode structure 20.
Consequently, spacers 19 and hard mask layer 18 may be partially lost during the formation of interconnection contact hole 50. As a result, gate electrode material 17 may be exposed and may be short-circuited by a conductive material formed later in interconnection contact hole 50.
To solve these problems, some conventional memory devices interpose etch stoppers between first insulating layer 30 and second insulating interlayer 40 to prevent first insulating interlayer 30 from being etched when bitline contact holes 45 are formed. A conventional memory device employing this technique is disclosed, for example, in U.S. Pat. No. 6,787,906 (the '906 patent).
In the '906 patent, etch stoppers are formed on first insulating layer 30. Accordingly, bitline contact holes 45 and storage node contact holes can be formed without further etching first insulating layer 30. However, the etch stoppers are also formed in core and peripheral region “B”, making it difficult to form interconnection contact hole 50. Since interconnection contact hole 50 penetrates first and second insulating layers 30 and 40, if the etch stoppers are interposed between first and second insulating interlayers 30 and 40, it is difficult to expose junction region 25b. 